View FDP047AN08_223731.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0
June 2004
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0
N-Channel PowerTrench(R) MOSFET 75V, 80A, 4.7m
Features
* rDS(ON) = 4.0m (Typ.), VGS = 10V, ID = 80A * Qg(tot) = 92nC (Typ.), VGS = 10V * Low Miller Charge * Low QRR Body Diode * UIS Capability (Single Pulse and Repetitive Pulse) * Qualified to AEC Q101
Formerly developmental type 82684
Applications
* 42V Automotive Load Control * Starter / Alternator Systems * Electronic Power Steering Systems * Electronic Valve Train Systems * DC-DC converters and Off-line UPS * Distributed Power Architectures and VRMs * Primary Switch for 24V and 48V systems
DRAIN (FLANGE)
SOURCE DRAIN SOURCE DRAIN GATE GATE
SOURCE DRAIN GATE
D
DRAIN (FLANGE) DRAIN (FLANGE)
G S
TO-220AB
FDP SERIES
TO-262AB
FDI SERIES
TO-247
FDH SERIES
MOSFET Maximum Ratings TC = 25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TC < 144oC, VGS = 10V) Continuous (TC = 25oC, VGS = 10V, with RJA = 62oC/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature 80 15 Figure 4 475 310 2.0 -55 to 175 A A A mJ W W/oC
o
Ratings 75 20
Units V V
C
Thermal Characteristics
RJC RJA RJA Thermal Resistance Junction to Case TO-220, TO-262, TO-247 Thermal Resistance Junction to Ambient TO-220, TO-262 (Note 2) Thermal Resistance Junction to Ambient TO-247 (Note 2) 0.48 62 30
oC/W o o
C/W C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2004 Fairchild Semiconductor Corporation
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0 Rev. C
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0
Package Marking and Ordering Information
Device Marking FDP047AN08A0 FDI047AN08A0 FDH047AN08A0 Device FDP047AN08A0 FDI047AN08A0 FDH047AN08A0 Package TO-220AB TO-262AB TO-247 Reel Size Tube Tube Tube Tape Width N/A N/A N/A Quantity 50 units 50 units 30 units
Electrical Characteristics TC = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 60V VGS = 0V VGS = 20V TC = 150oC 75 1 250 100 V A nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250A ID = 80A, VGS = 10V rDS(ON) Drain to Source On Resistance ID = 37A, VGS = 6V ID = 80A, VGS = 10V, TJ = 175oC 2 4 V 0.0040 0.0047 0.0058 0.0087 0.0082 0.011
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge (VGS = 10V) VDD = 40V, ID = 80A VGS = 10V, RGS = 3.3 18 88 40 45 160 128 ns ns ns ns ns ns VDS = 25V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 2V VDD = 40V ID = 80A Ig = 1.0mA 6600 1000 240 92 11 27 16 21 138 17 pF pF pF nC nC nC nC nC
Switching Characteristics
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 80A ISD = 40A ISD = 75A, dISD/dt = 100A/s ISD = 75A, dISD/dt = 100A/s 1.25 1.0 53 54 V V ns nC
Notes: 1: Starting TJ = 25C, L = 0.232mH, IAS = 64A. 2: Pulse Width = 100s
(c)2004 Fairchild Semiconductor Corporation
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0 Rev. C
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0
Typical Characteristics TC = 25C unless otherwise noted
1.2 200 CURRENT LIMITED BY PACKAGE ID, DRAIN CURRENT (A) 0 25 50 75 100 125 150 175 160
POWER DISSIPATION MULTIPLIER
1.0
0.8
120
0.6
80
0.4
0.2
40
0 TC , CASE TEMPERATURE (oC)
0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs Case Temperature
2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Case Temperature
ZJC, NORMALIZED THERMAL IMPEDANCE
PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
SINGLE PULSE 0.01 10-5 10-4
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: VGS = 10V I = I25 175 - TC 150
1000 IDM, PEAK CURRENT (A)
100
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
50 10-5
10-4
10-3
10-2 t, PULSE WIDTH (s)
10-1
100
101
Figure 4. Peak Current Capability
(c)2004 Fairchild Semiconductor Corporation
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0 Rev. C
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0
Typical Characteristics TC = 25C unless otherwise noted
2000 1000 10s IAS, AVALANCHE CURRENT (A) 100s ID, DRAIN CURRENT (A) 100 500 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 STARTING TJ = 25oC
1ms 10ms
10
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TC = 25oC
10
DC
1
STARTING TJ = 150oC
0.1 0.1
1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 .01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100
Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching Capability
150
150 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A)
VGS = 10V 120 VGS = 6V 90
VGS = 7V
120 ID , DRAIN CURRENT (A)
90 TJ = 175oC 60 TJ = 25oC 30 TJ = -55oC
60 VGS = 5V 30 TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
0 4.0
0 4.5 5.0 5.5 VGS , GATE TO SOURCE VOLTAGE (V) 6.0 0 0.5 1.0 VDS , DRAIN TO SOURCE VOLTAGE (V) 1.5
Figure 7. Transfer Characteristics
7 DRAIN TO SOURCE ON RESISTANCE(m) NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 6 VGS = 6V 5 2.5
Figure 8. Saturation Characteristics
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0
1.5
4 VGS = 10V 3 0 20 40 ID, DRAIN CURRENT (A) 60 80
1.0
VGS = 10V, ID = 80A 0.5 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200
Figure 9. Drain to Source On Resistance vs Drain Current
Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature
(c)2004 Fairchild Semiconductor Corporation
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0 Rev. C
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0
Typical Characteristics TC = 25C unless otherwise noted
1.2 VGS = VDS, ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.10 1.15 ID = 250A
NORMALIZED GATE THRESHOLD VOLTAGE
1.0
1.05
0.8
1.00
0.6
0.95
0.4 -80
-40
0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
200
0.90 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature
10000 CISS = CGS + CGD C, CAPACITANCE (pF) COSS CDS + CGD
Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 40V 8
6
1000 CRSS = CGD
4 WAVEFORMS IN DESCENDING ORDER: ID = 80A ID = 10A 0 25 50 Qg, GATE CHARGE (nC) 75 100
2
VGS = 0V, f = 1MHz 100 0.1 0 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 75
Figure 13. Capacitance vs Drain to Source Voltage
Figure 14. Gate Charge Waveforms for Constant Gate Currents
(c)2004 Fairchild Semiconductor Corporation
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0 Rev. C
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG IAS VDD VDD tP VDS
+
IAS 0.01 0 tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS VDD L VGS VDS Qg(TOT) VGS
VGS = 10V
+
VDD DUT Ig(REF) VGS = 2V 0
Qgs2
Qg(TH) Qgs Ig(REF) 0 Qgd
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH
90% 50%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
(c)2004 Fairchild Semiconductor Corporation
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0 Rev. C
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0
PSPICE Electrical Model
.SUBCKT FDP047AN08A0 2 1 3 ; CA 12 8 1.5e-9 CB 15 14 1.5e-9 CIN 6 8 6.4e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 82.3 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.81e-9 LSOURCE 3 7 4.63e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 9e-4 RGATE 9 20 1.36 RLDRAIN 2 5 10 RLGATE 1 9 48.1 RLSOURCE 3 7 46.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 2.3e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1 RLGATE CIN
rev March 2002
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED 5 DRAIN 2
RSLC2
5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 -
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10))} .MODEL DBODYMOD D (IS = 2.4e-11 N = 1.04 RS = 1.76e-3 TRS1 = 2.7e-3 TRS2 = 2e-7 XTI=3.9 CJO = 4.35e-9 TT = 1e-8 M = 5.4e-1) .MODEL DBREAKMOD D (RS = 1.5e-1 TRS1 = 1e-3 TRS2 = -8.9e-6) .MODEL DPLCAPMOD D (CJO = 1.35e-9 IS = 1e-30 N = 10 M = 0.53) .MODEL MMEDMOD NMOS (VTO = 3.7 KP = 9 IS =1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.36) .MODEL MSTROMOD NMOS (VTO = 4.4 KP = 250 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 3.05 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.36e1 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = -9e-7) .MODEL RDRAINMOD RES (TC1 = 1.9e-2 TC2 = 4e-5) .MODEL RSLCMOD RES (TC1 = 1.3e-3 TC2 = 1e-5) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -6e-3 TC2 = -1.9e-5) .MODEL RVTEMPMOD RES (TC1 = -2.4e-3 TC2 = 1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4.0 VOFF= -1.5) VON = -1.5 VOFF= -4.0) VON = -1.0 VOFF= 0.5) VON = 0.5 VOFF= -1.0)
(c)2004 Fairchild Semiconductor Corporation
+
DBODY
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0 Rev. C
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0
SABER Electrical Model
REV March 2002 template FDP047AN08A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 2.4e-11, n1 = 1.04, rs = 1.76e-3, trs1 = 2.7e-3, trs2 = 2e-7, xti = 3.9, cjo = 4.35e-9, tt = 1e-8, m = 5.4e-1) dp..model dbreakmod = (rs = 1.5e-1, trs1 = 1e-3, trs2 = -8.9e-6) dp..model dplcapmod = (cjo = 1.35e-9, isl =10e-30, nl =10, m = 0.53) m..model mmedmod = (type=_n, vto = 3.7, kp = 9, is =1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 4.4, kp = 250, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 3.05, kp = 0.03, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -1.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -4.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.0)
LDRAIN DPLCAP 5 RLDRAIN
c.ca n12 n8 = 1.5e-9 c.cb n15 n14 = 1.5e-9 c.cin n6 n8 = 6.4e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod
ESG
10 RSLC1 51 RSLC2 ISCL 6 8 + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 6 MSTRO 8 EVTHRES + 19 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11 DBODY
DRAIN 2
i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 4.81e-9 l.lsource n3 n7 = 4.63e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -9e-7 res.rdrain n50 n16 = 9e-4, tc1 = 1.9e-2, tc2 = 4e-5 res.rgate n9 n20 = 1.36 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 48.1 res.rlsource n3 n7 = 46.3 res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.3e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.4e-3, tc2 = 1e-6 res.rvthres n22 n8 = 1, tc1 = -6e-3, tc2 = -1.9e-5 spe.ebreak n11 n7 n17 n18 = 82.3 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1
S1A 12 S1B CA 13 + EGS 6 8 13 8 S2A 14 13 S2B
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE RBREAK 17 18 RVTEMP CB + EDS 5 8 8 RVTHRES 14 IT VBAT + 22 19
15
equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10)) } }
(c)2004 Fairchild Semiconductor Corporation
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0 Rev. C
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0
SPICE Thermal Model
REV 23 March 2002 FDP047AN08A0T CTHERM1 th 6 6.45e-3 CTHERM2 6 5 3e-2 CTHERM3 5 4 1.4e-2 CTHERM4 4 3 1.65e-2 CTHERM5 3 2 4.85e-2 CTHERM6 2 tl 1e-1 RTHERM1 th 6 3.24e-3 RTHERM2 6 5 8.08e-3 RTHERM3 5 4 2.28e-2 RTHERM4 4 3 1e-1 RTHERM5 3 2 1.1e-1 RTHERM6 2 tl 1.4e-1
th
JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDP047AN08A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 6.45e-3 ctherm.ctherm2 6 5 = 3e-2 ctherm.ctherm3 5 4 = 1.4e-2 ctherm.ctherm4 4 3 = 1.65e-2 ctherm.ctherm5 3 2 = 4.85e-2 ctherm.ctherm6 2 tl = 1e-1 rtherm.rtherm1 th 6 = 3.24e-3 rtherm.rtherm2 6 5 = 8.08e-3 rtherm.rtherm3 5 4 = 2.28e-2 rtherm.rtherm4 4 3 = 1e-1 rtherm.rtherm5 3 2 = 1.1e-1 rtherm.rtherm6 2 tl = 1.4e-1 }
RTHERM3 CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2004 Fairchild Semiconductor Corporation
FDP047AN08A0 / FDI047AN08A0 / FDH047AN08A0 Rev. C
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM ActiveArrayTM BottomlessTM CoolFETTM CROSSVOLTTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM
FACT Quiet SeriesTM FAST(R) FASTrTM FPSTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM I2CTM i-LoTM
Across the board. Around the world.TM The Power Franchise(R) Programmable Active DroopTM
ImpliedDisconnectTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM
POPTM Power247TM PowerSaverTM PowerTrench(R) QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER(R) SMART STARTTM SPMTM
StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TINYOPTOTM TruTranslationTM UHCTM UltraFET(R) VCXTM
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I11

▲Up To Search▲

Price & Availability of FDP047AN08

	To Download FDP047AN08 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .